1. Field of the Invention
This invention relates generally to design verification. More particularly, this invention relates to evaluation of a processor implementation for compliance with its specification.
2. Description of the Related Art
TABLE 1Acronyms and AbbreviationsARMAdvanced RISC MachineASICApplication-Specific Integrated CircuitCPUCentral Processing UnitCSPConstraint Satisfaction ProblemDAGDirected Acyclic GraphI/OInput/OutputIEEEInstitute of Electrical and ElectronicsEngineersISAInstruction Set ArchitectureOpcodeOperation CodeRISCReduced Instruction Set ComputerSoCSystem on a ChipWFEWrong Edge and False Edge Misinterpretations
An important aspect of designing a computer processor is testing the design thoroughly, in order to assure that the design complies with desired architectural specifications. This can be achieved either by a formal proof or by exhaustive simulation. However, state of the art formal techniques and the complexity of processors render the formal approach unfeasible for large industrial applications. Moreover, exhaustive simulation is impossible, as the test space is enormous. In practice, design verification is carried out by simulating a relatively small subset of selected test programs. These are run through a design simulation model, and the results are compared with the output predicted by an architecture simulation model.
Test program generators are basically sophisticated software engines, which are used to create numerous test cases to be executed by the processor implementation under test. By appropriate configuration, it is possible for test generation to be focused on very specific ranges of conditions, or broadened to cover a wide range of logic. Today, large numbers of test cases can be created automatically in the time that a single test case could be written manually, as was done prior to the advent of test case generators.
An example of a conventional test program generator is the IBM tool, Genesys, which is disclosed in the document Model-Based Test Generation for Process Design Verification, Y. Lichtenstein et al., Sixth Innovative Applications of Artificial Intelligence Conference, August 1994, pp. 83-94. An updated version, of Genesys, known as Genesys-Pro, is a generic random test generator, targeted at the architectural level and applicable to any architecture.
The importance of validating architecture compliance has increased in recent years, as complex hardware designs have shifted from custom ASICs toward SoC designs, which include ready-made components (“cores”). One of the immediate outcomes of this trend is a very strong drive towards standardization at all levels. In this context, there is a growing tendency to use well-established and recognized processor architectures.
Consequently, many companies that build processor-based SoCs nowadays choose to design a microprocessor that implements an existing and proven architecture that is commercially available. These companies, along with the architecture owner, obviously have a strong incentive to ensure that the design complies with its specification. In short, the need for compliance validation has increased.